1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device with a cavity interposed between wirings formed on the same layer.
2. Description of the Related Art
There have arisen a problem of a wiring delay together with progress in miniaturization of a semiconductor device. As for causes of the wiring delay, there are a resistance of wiring and capacitance between wirings. In order to reduce a resistance of a wiring, adopting a suitable material for a wiring and thickening a film for wiring are considered. However, thickening of a film for wiring would be like swimming against the current of miniaturization of the semiconductor device, and a capacitance between wirings comes to increase as well. Accordingly, it is desired a method for reducing a capacitance between wirings, especially, formed on the same layer, while securing reliability of the wiring. Methods are under examination in which a dielectric constant of an insulation film between wirings is lowered by use of an oxide film mixed with fluorine or an organic interlayer film as the insulation film between the wirings. However, as a distance between wirings becomes narrower, an insulation film with a lower dielectric constant is more in demand.
Methods of fabricating a semiconductor device containing an insulation film as a layer in which a cavity is interposed between wirings formed on the same layer have been proposed (Japanese Examined Patent Publication (Kokoku) No. Hei 7-114236 and Japanese Unexamined Patent Publication (Kokai) No. Sho 62-5643). FIG. 1 is a sectional view showing a method of fabricating a semiconductor device disclosed in the Japanese Examined Patent Publication No. Hei 7-114236. In a conventional method of fabricating a semiconductor device described in this publication, first, a first insulation film 16 is formed on a semiconductor substrate 15. Subsequently, two wirings 17 are formed on the first insulation film 16 separated from each other by patterning. Furthermore, a second insulation film 18 is formed on and between the wirings 17 by means of a sputtering method. On this occasion, a cavity 19 is formed in the second insulation film 18 between the wirings 17. In the semiconductor device fabricated as mentioned above, since the cavity 19 has a lower dielectric constant than that of the second insulation film 18, a capacitance between the wirings 17 is reduced to a lower value, compared with the case where a cavity 19 is not formed. In the above mentioned semiconductor device, however, an area where a cavity is not formed between wirings 17 remains and thereby a capacitance in the area is still not reduced. Therefor, the capacitance between wirings 17 is not reduced enough.
On the other hand, in a conventional method of fabrication a semiconductor device disclosed in the Japanese Unexamined Patent Publication No. Sho 62-5643, wirings are first formed on an insulation film. On formation of the wirings, an insulation film between the wirings is over-etched. An interlayer insulation film is formed between the wirings formed on the same insulation film by means of a common CVD method, and, at the same time, a cavity is formed in the interlayer insulation film. In the semiconductor device fabricated as mentioned above, since the interlayer insulation film containing the cavity which works as a perfect shield between the wirings is formed, the capacitance between the wirings is more reduced, compared with the semiconductor device described in the Japanese Examined Patent Publication No. Hei 7-114236. However, locations and sizes of cavities are hard to control by means of the common CVD method. For example, in the case where an interlayer insulation film lying on the lower side of aluminum wirings is over-etched to a great extent, an aspect ratio of a space between the wirings becomes larger in excess and thereby a cavity to work as a perfect shield between the wirings can not be formed in some cases. Accordingly, reduction of capacitance is not enough. In a method in which etching of an insulation film is effected taking a resist film as a mask, since a selectivity between the insulation film and the resist film is not enough, the upper end corners of aluminum wirings are etched off during etching the insulation film.
A method is proposed in which a cavity is formed between first wirings on the same layer taking a second wiring as a mask which is formed above the first wirings (Japanese Unexamined Patent Publication (Kokai) No. Hei 3-196662). FIG. 2A is a plan view showing a method of fabricating a semiconductor device disclosed in the Japanese Unexamined Patent Publication No. Hei 3-196662. FIG. 2B is a sectional view taken along the A--A in FIG. 2A and FIG. 2C is a sectional view taken along the B--B in FIG. 2A. In a conventional method of fabricating a semiconductor device disclosed in the publication, two lower wirings 21 are first formed on a flat insulation film 25 in parallel. An interlayer insulation film 22 is then formed all over the exposed surface. An upper wiring 20 located in a perpendicular relation to the lower wirings 21 is formed on the interlayer insulation film 22. Thereafter, the interlayer insulation film 22 is etched by means of a RIE method taking the upper wiring 20 and the lower wirings 21 as a mask. As a result, as shown in FIG. 2B, the interlayer insulation film 22 under the upper wiring 20 is not etched, but as shown in FIG. 2C, the insulation film 25 is partly over-etched. Subsequently, a surface protecting film 24 is formed all over the exposed surface. The surface protecting film 24 is omitted in FIG. 2A. In a semiconductor device fabricated in such a manner, since a cavity 23 is interposed between the lower wirings 21 except an area under the upper wiring 20, a capacitance between the lower wirings 21 is reduced.
A size, location and the like of the cavity 23, however, are dependent on a layout of the upper wiring 20 and therefore no cavity is formed under the upper wiring 20. For this reason, the capacitance between the lower layer wirings 21 becomes uneven and thus the overall reduction of capacitance is not enough. Moreover, unless an etching condition with an enough selectivity is selected when the interlayer insulation film 22 is etched, the lower wirings 21 are partly etched and, as a result, there arises a problem that the lower wirings 21 are narrower and have a higher resistance than desired.